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![]() Model checking Academia Knowledge Logic Formal methods Temporal logic Mathematical logic Formal verification Rajeev Alur Formal sciences Model checkers Science | Add to Reading List |
![]() | Results and Analysis of SyGuS-Comp’15 Rajeev Alur Dana Fisman University of PennsylvaniaDocID: 1xTYH - View Document |
![]() | Safe Schedulability of Bounded-Rate Multi-Mode Systems Rajeev Alur ˇ Forejt VojtechDocID: 1xTB7 - View Document |
![]() | The 4th Competition on Syntax-Guided Synthesis Rajeev Alur, Dana Fisman, Rishabh Singh and Armando Solar-LezamaDocID: 1xTaX - View Document |
![]() | 1 Regular Functions and Cost Register Automata Rajeev Alur∗ , Loris D’Antoni∗ , Jyotirmoy Deshmukh† , Mukund Raghothaman∗ and Yifei Yuan∗ ∗ University of Pennsylvania † Toyota Technical Center (Invited PDocID: 1vnBd - View Document |
![]() | NetEgg: Programming Network Policies by Examples Yifei Yuan Rajeev Alur Boon Thau LooDocID: 1v397 - View Document |