Back to Results
First PageMeta Content
Cache coherency / Distributed computing architecture / Cache coherence / Cache / Shared memory / Multi-core processor / Coherence / MOESI protocol / Consistency model / Concurrent computing / Computing / Parallel computing


CACHE COHERENCE TECHNIQUES FOR MULTICORE PROCESSORS by
Add to Reading List

Document Date: 2009-02-13 04:23:23

Open Document

File Size: 2,01 MB

Share Result on Facebook

City

Flat Directory / /

Company

Multiple-CMP Systems / Computer Sciences / Wisconsin Computer Architecture Affiliates / Computer Systems Laboratory / Building Larger Systems / /

Currency

AMD / /

Event

FDA Phase / /

Facility

Computer Systems Laboratory / UNIVERSITY OF WISCONSIN / /

IndustryTerm

multicore chips / multicore chip / hierarchical coherence protocol / flat coherence protocols / directory protocol / hierarchical coherence protocols / memory systems / cache coherence protocols / tiled multicore chip / cache coherence protocol / /

Organization

National Science Foundation / Graduate school / UNIVERSITY OF WISCONSIN / /

Person

Yasuko Watanabe / David Wood / Matt Allen / Derek Hower / Mary Vernon / Carl Mauer / Brad Beckmann / Natalie Enright / Jayaram Bobba / Philip Wells / Remzi Arpaci-Dusseau / Michelle Moravan / Nidhi Aggarwal / Dan Sorin / Milo Martin / Allison Holloway / Dana Vantrease / Luke Yen / Kathleen / Mike Swift / Dan Gibson / Mark Hill / Tom Reps / Guri Sohi / Min Xu / Somesh Jha / Kevin Moore / Susan Horwitz / Andy Phelps / Mikko Lipasti / Kyle Nesbit / Bart Miller / Ben Liblit / Michael R. Marty / /

Position

advisor / director of the Multifacet project / golfer / experienced engineer / /

Product

M-CMPs / /

ProvinceOrState

Wisconsin / /

Technology

MOESI Intra-CMP Protocol / MOESI Inter-CMP Protocol / two directory-based protocols / 5.2 Embedding Ring Protocols / multicore chips / CMP system / existing flat coherence protocols / 3.1 Level-One Intra-VM Directory Protocol / shared memory / cache coherence protocol / hierarchical coherence protocols / CMP / tiled multicore chip / cache coherence protocols / hierarchical coherence protocol / 5.3 Hierarchical Ring Protocols / 2-level directory protocol / caching / simulation / multicore chip / /

SocialTag