<--- Back to Details
First PageDocument Content
Negated AND gate / OR gate / Inverter / AND gate / Canonical form / Boolean algebra / CMOS / Series / Logical effort / Logic gates / Electronic engineering / Electronics
Date: 2001-10-01 00:13:10
Negated AND gate
OR gate
Inverter
AND gate
Canonical form
Boolean algebra
CMOS
Series
Logical effort
Logic gates
Electronic engineering
Electronics

Add to Reading List

Source URL: cva.stanford.edu

Download Document from Source Website

File Size: 34,44 KB

Share Document on Facebook

Similar Documents

PDF Document

DocID: 1xs12 - View Document

PDF Document

DocID: 1x2IS - View Document

DOC Document

DocID: 1wpoX - View Document

A 23mW Face Recognition Accelerator in 40nm CMOS with Mostly-Read 5T Memory Dongsuk Jeon1,2, Qing Dong1, Yejoong Kim1, Xiaolong Wang3, Shuai Chen3, Hao Yu3, David Blaauw1, Dennis Sylvester1 1 University of Michigan, MI;

DocID: 1vrMD - View Document

  CELL CULTURE COURSE PROGRAM September 13, 2014   08:00-08:45 Cultivation of cells, passaging, Medium Preparation and Preparation for experiments Theoretic 09:00-09:45 Cultivation of cells, passaging, Medium Preparati

DocID: 1vnJh - View Document