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Document Date: 2006-08-04 16:31:49Open Document File Size: 285,28 KBShare Result on FacebookCityPortland / San Jose / /CompanyIntel corporation / AMD / /CountryUnited States / / /Facilitycdll.LoadLibrary(util.find library / C library / Computer Science University of Illinois / /IndustryTermsoftware framework / hardware transactional memory infrastructure / transactional memory systems / host applications / multiprocessor systems / virtual memory hardware / software-based parallelism / in-cache management / software transactional memory / transactional memory infrastructure / invalidation-based cache coherence protocol / transactional memory-aware operating systems / software reliability / event-based applications / mainstream systems / software-based counterparts / potential general solution / simulation infrastructure / physical processors / /OperatingSystemLinux / POSIX / /OrganizationNational Science Foundation / Lightweight Dynamic Language Evolution Nicholas Riley Craig Zilles Department / University of Illinois / /PersonSamuele Pedroni / Greg Stein / Carl Friedrich Bolz / B. T. Lewis / V / F. Drake / Jr. / Armin Rigo / Transactional Python / Fedora Core / Michael Hudson / M. J. Moravan / M. Herlihy / V / Nicholas Riley Craig Zilles / / /PositionGlobal Interpreter / collector / Boehm-Demers-Weiser conservative garbage collector / Standard Interpreter / functional interpreter / PyPy garbage collector / General / bytecode interpreter / interpreter / author / garbage collector / writer / PyPy interpreter / programmer / /ProgrammingLanguageJava / Erlang / C / Python / Tcl / Perl / CPython / Ruby / C++ / RPython / /ProvinceOrStateOregon / California / /RadioStationCore 3 / /Technologyfour physical processors / Functional Programming / RAM / existing invalidation-based cache coherence protocol / Linux / API / Perl / operating system / html / operating systems / 4 processors / Java / HTTP / simulation / virtual memory / /URLhttp /SocialTag |