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SHARK A Realizable Special Hardware Sieving Device for Factoring 1024-bit Integers Jens Franke1 , Thorsten Kleinjung1 , Christof Paar2 , Jan Pelzl2 , Christine Priplata3 , and Colin Stahlke3 1
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Document Date: 2008-09-15 00:54:55

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File Size: 221,59 KB

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City

Bonn / /

Company

EDIZONE GmbH / /

Country

Germany / /

Currency

USD / /

/

Facility

University of Bonn / Horst G¨ ortz Institute / /

IndustryTerm

purpose hardware / conventional processors / evaluation processor / cryptographic protocols / proposed sieving device / software experiments / chip / lattice sieving device / hardware devices / large memory chip / /

Organization

Horst G¨ ortz Institute for IT Security / Department of Mathematics / FF + / ASIC / University of Bonn / /

Position

General / Introduction The General / evaluator / /

ProvinceOrState

Manitoba / /

Technology

evaluation processor / cache memory / separate chip / RAM / ASIC / extremely large memory chip / /

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