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CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging∗ Smruti R. Sarangi, Brian Greskamp, and Josep Torrellas Department of Computer Science, University of Illinois http://iacoma.cs.uiuc.edu Abstract
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Document Date: 2006-04-04 17:13:03

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File Size: 184,86 KB

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Company

Checkpoint / IBM / Cambridge University Press / Sun Microsystems / Agilent technologies / Intel 82801ER I/O / Intel E7525 Memory / Intel 82801EB I/O / RTL / Intel / Agilent Systems / /

Facility

Checkpoint Restoration / CADRE checkpoint / Checkpoint State / Checkpoint Initiation / /

IndustryTerm

intensive network / human-interface devices / scientific applications / techniques that ease hardware / speed processors / base unmodified hardware / architectural solution / test equipment / in-house hardware / multiprocessor chip / WEB JBB OMP INT FP / deterministic processing / in-order processors / similar hardware / software developers / WEB disk JBB OMP network / out-of-order processors / memory systems / deployed software / processor chip / real-time software testing / correct processing time / message processing / software debugging / deterministic message processing / technology roadmap / memory chips / WEB JBB disk OMP network INT FP Server Measured Dual-processor / replay protocol / multiprocessor server / board-level computer hardware / modest hardware / resume computing / workloads WEB / cycledeterministic systems / /

OperatingSystem

Linux / SuSE Linux / /

Organization

Cambridge University / National Science Foundation / Josep Torrellas Department of Computer Science / University of Illinois / Environmental Protection Agency / /

Person

Synchronizer Proc / Processor / Brian Greskamp / /

Position

IO Controller / guard / CADRE Controller / I/O controller / head / engineer / supervisor / Memory Log Controller / designer / memory controller / CADRE Controller CADRE Controller / Controller / /

Product

Cowon D2+ Portable Audio Device / /

ProgrammingLanguage

Java / FP / Verilog / /

RadioStation

6 CKPT / 3 CKPT / 1 CKPT / 4 CKPT / /

Technology

detailed algorithm / McKinley processor / high-speed processors / multiprocessor chip / production processor / 4 processor / Linux / two processors / Protocol The replay protocol / JTAG / Itanium-2 processor / proposed algorithms / second processor / in-order processors / processor chip / shared memory / replay protocol / semiconductors / Verilog / HyperTransport protocol / Java / Lamport algorithm / synchronous DRAM memory chips / SDRAM / 500 60 50 40 30 20 10 0 WEB JBB disk OMP network INT FP Server Measured Dual-processor / checkpointing protocol / 6-issue out-of-order processors / simulation / 8 7 BUSRST Processor / DRAM chip / Pentium-M processor / /

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http /

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