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City Macungie / / Company IBM / LSI Logic / Synopsys / IEEE 754 Working Group / International Business Machines / RTL / Potential Speedup Using Decimal Floating-Point Hardware / / Currency pence / / / Facility Michael Schulte University of Wisconsin / Synopsys’s DesignWare IP library / DesignWare library / / IndustryTerm final product / financial and commercial applications / iterative algorithm / rounded intermediate product / mediate product / partial-products / software implementations / banking / final corrective partial product / extra hardware / fractional product / extra corrective partial product / intermediate product / partial products / decimal partial products / truncated intermediate product / / Organization University of Wisconsin / Decimal Arithmetic Unit / / Person Elisardo Antelo / Brian Hickmann / Paolo Montuschi / Decimal Arithmetic / Alvaro Vazquez / Max Num / Decimal Arithmetic Testcases / Andrew Krioukov / / / Position guard / CPA / g=guard / General / / Product DesignWare / FPgen tool / FPgen / / ProgrammingLanguage Verilog / FP / / ProvinceOrState Oregon / Pennsylvania / / PublishedMedium IEEE Transactions on Computers / / Technology Verilog / Three Rounding Algorithms / iterative algorithm / implemented using Verilog / / URL http / SocialTag 
A Parallel IEEE P754 Decimal Floating-Point Multiplier Brian Hickmann, Andrew Krioukov, and Michael Schulte University of Wisconsin - Madison Dept. of Electrical and Computer Engineering Madison, WI 53706 {bjhickmann, kr