Higher Computing Computer Structure

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Date: 2011-04-01 05:00:02 Bus Computer Computer buses CPU multiplier Front-side bus Computer hardware Motherboard Central processing unit		Higher Computing Computer Structure Add to Reading List Source URL: www.alfordacademy.aberdeenshire.sch.uk Download Document from Source Website File Size: 30,50 KB Share Document on Facebook

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	CPU Speed = 125.33Mhz, Memory Bus Speed = 62.67Mhz (Period = 15.96ns) Reference Oscillator = 29.4912Mhz, PLL Multiplier = 17 (ND = 16), PLL Output Divider = 2 (FS = 1) Component Register Name Register Mnemonic Global SDR DocID: S60k - View Document