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Electronic design / Electronic design automation / Safety / Field-programmable gate array / Altera / Nios II / Semiconductor intellectual property core / Logic synthesis / Disk partitioning / Electronic engineering / Electronics / Digital electronics


FPGA -based Safety Separation Design Flow for Rapid IEC[removed]Certification
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Document Date: 2014-06-24 11:01:32

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File Size: 505,24 KB

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City

San Jose / /

Company

Quartus II Software / Design Hierarchy Partition B Partition Top Altera Corporation / Safety IP Core Altera Corporation / BLDC / Altera Corporation / IEC 61508 Certification Send Feedback Altera Corporation / OpenCore Plus / /

IndustryTerm

Industrial machinery manufacturers / changes to any products / semiconductor products / /

Organization

U.S. Patent and Trademark Office / Logical Design Partitions FPGA Host Development Board / /

Person

Stage Logical / /

Position

designer / text editor / model / /

ProgrammingLanguage

DC / /

ProvinceOrState

California / Ontario / /

Technology

semiconductor / FPGA / DDR SDRAM / FOC algorithm / ADC / Chip design / Multiaxis Motor Control Power Board Motor Drive System Monitor DC Link Monitor ADC Related Information Drive On-Chip / DSP / /

URL

www.altera.com/common/legal.html / www.altera.com / /

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