| Document Date: 2013-07-27 22:49:15 Open Document File Size: 576,90 KBShare Result on Facebook
Company RTL / System Design Ricardo E. Gonzalez Tensilica Inc. / TSMC / / Facility foundry Complete / Xtensa V1.5 Implementation Pipeline / / IndustryTerm software configured/extended / / OperatingSystem GNU / / Position manager GNU C++ Compiler GNU / / ProgrammingLanguage ANSI C / C++ / Tensilica Instruction Extension / Verilog / C / / Technology DSP / ANSI C / VHDL / image compression / CMP / Verilog / /
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