2003 Workshop on Compact Modeling Unified RLC Model for On-Chip Interconnects Sang-Pil Sim and Cary Y. Yang Microelectronics Lab., Santa Clara University, CA, - Electromagnetic field solver - Document - PDFSEARCH.IO

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	2003 Workshop on Compact Modeling Unified RLC Model for On-Chip Interconnects Sang-Pil Sim and Cary Y. Yang Microelectronics Lab., Santa Clara University, CA, Add to Reading List Document Date: 2010-03-19 15:29:00 Open Document File Size: 1,39 MB Share Result on Facebook Company SP1 W S COMB1 Metal / / Facility University On-Chip Interconnect Outline / University Capacitance Model Extraction Results / University Capacitance Model Quasi-3D Extraction Using Weff / University Outline / Santa Clara University / University Capacitance Model On-Chip Capacitance / University B C Ctotal / University On-Chip Interconnect Wire / / IndustryTerm performance-driven chip / / Organization IMD / Santa Clara University / Cary Y. Yang Microelectronics Lab. / / Person Yang Microelectronics / Cary Y. Yang / Sang-Pil Sim / / Technology Conclusions Santa Clara University Capacitance Model On-Chip / Conclusion Santa Clara University On-Chip / performance-driven chip Santa Clara University On-Chip / 1 0.1 250 180 130 90 65 45 32 ~15ps Process Technology / / SocialTag Electronic design automation Integrated circuits Capacitance Electricity Electromagnetic field solver Parasitic extraction Electromagnetism Electronic engineering Electronics

2003 Workshop on Compact Modeling Unified RLC Model for On-Chip Interconnects Sang-Pil Sim and Cary Y. Yang Microelectronics Lab., Santa Clara University, CA,Add to Reading List