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Origin System Design Methodology and Experience: 1M-gate ASICs and Beyond Ásgeir Th. Eiríksson, John Keen, Alex Silbey, Swami Venkataraman, Michael Woodacre Silicon Graphics Inc., Mountain View, CA Abstract.
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Document Date: 2008-04-15 16:23:14

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Mountain View / /

Company

IBM / MIPS technologies / Silicon Graphics / HLD Systems / Michael Woodacre Silicon Graphics Inc. / SGI / FSMs / Synopsys / RTL / /

Country

Belgium / /

Event

Business Partnership / FDA Phase / /

IndustryTerm

simulation tools / ccNUMA cache coherence protocol / cache coherency protocol / static timing analysis tools / synthesis tool / macro expansion tool / virtual router / multi-hour processing times / particular processor / verified cache coherence protocol / credit size management / multiprocessor systems / coherence protocol / cache coherence protocols / metal / interconnect network / unrealizable chip / gate standard cell chip / router chips / data management / formal verification tool / layout tools / cache coherence protocol / large chip / /

Movie

Divide and conquer / /

OperatingSystem

UNIX / /

Organization

ASIC / /

Person

Alex Petruncola / Ken L. McMillan / Curt McDowell / Jim Laudon / Tuan Tran / Pat Conway / Dave Koller / Mike McNamara / Ken Jacobsen / Dawn Maxon / Todd Massey / Thom Derenthal / Alex Silbey / Y BDD / Martin Frankel / Dave Parry / Steve Whitney / George Kaldani / John Keen / Chuck Narad / Dick Hessel / Ron Nikel / Steve Padnos / Ken McMillan / Rick Paul / Peter Ostrin / Dave Harmon / Bob Alfieri / Stan Bailes / Gutrum Wolski / Eric Williams / Rich Weber / Dan Lenoski / Joanne Allen / Eiriksson McMillan / Ben Fathi / Mike Galles / /

Position

Modify Abstract Specification specification document translation translation smv system model / Symbolic Model / node controller / verilog model for any unit / feed-forward / Memory/Directory controller / logic designer / /

Product

Verilog PLI / Einstimer / SN0 / R10000 / /

ProgrammingLanguage

C / Verilog / /

ProvinceOrState

Wisconsin / Maryland / /

Technology

design verification / PLI virtual router / 2000 Hub chip / particular processor / unrealizable chip / virtual router / R10000 processors / verilog protocol / router chips / UNIX / two processors / SysAD protocol / large chip / perl / operating system / shared memory / cache coherence protocol / Spider router / 1 Hub Chip / Hub chip / cache coherence protocols / ASIC / cache coherency protocol / 4 processors / verilog / load balancing / XIO protocol / flow control / 6 ported router / formally verified cache coherence protocol / ASCII / 32 processor / coherence protocol / Hub chips / http / SDRAM / simulation / SGI SPIDER chip / cell chip / ccNUMA cache coherence protocol / /

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http /

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