| Document Date: 2006-02-17 04:36:19
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City Zurich / / Company Peter Luethi Integrated Systems Laboratory / Integrated Systems Laboratory / the AES / / Country Switzerland / / Currency USD / / IndustryTerm energy consumption / consumed on-chip / software evaluations / hardware designer / given hardware / cryptographic algorithms / few styles/technologies / eSTREAM candidate algorithms / cryptographic hardware / on-chip communications / backbone routers / area/energy consumption/design / Off-chip communications / correct hardware / cryptographic algorithm / stream cipher algorithms / Synthesis tools / candidate algorithms / algorithms / time/circuit area/operation speed/energy consumption / data processing rate / / Organization FPGA / ASIC / / Person Frank K. Gürkaynak / / Position algorithm designer / hardware designer / Implementation Errors The hardware designer / designer / cryptographic algorithm designer / representative / / ProgrammingLanguage Verilog / / Technology Encryption / stream cipher algorithms / FPGA / candidate algorithms / Cryptography / ASIC / backbone routers / relatively few styles/technologies / 34 algorithms / eventually eight seven eSTREAM candidate algorithms / 2.2 Cryptographic Properties Algorithms / Verilog / One algorithm / 30 candidate algorithms / secret key / 2.3 Applications Cryptographic algorithms / same algorithm / 0.25 µm CMOS technology / VHDL / consumed on-chip / cryptographic algorithm / all 34 candidate algorithms / two algorithms / implemented using a 0.25 µm CMOS technology / /
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Recommendations for Hardware Evaluation of Cryptographic Algorithms Frank K. Gürkaynak, Peter Luethi Integrated Systems Laboratory, ETH Zurich CH-8092 Switzerland Abstract. At the SASC 2006 three papers on hardware impl