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Dynamic random-access memory / Scheduling / CAS latency / Memory controller / Latency / SDRAM latency / GDDR5 / CPU cache / Random-access memory / Computer memory / Computer hardware / Computing


Managing DRAM Latency Divergence in Irregular GPGPU Applications Niladrish Chatterjee∗†§ , Mike O’Connor†k§ , Gabriel H. Loh‡, Nuwan Jayasena‡ and Rajeev Balasubramonian∗ ∗ University of Utah † NVIDI
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Document Date: 2014-08-15 10:13:33


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