Dynamic Budgeting for Settling DRAM Contention of Co-running Hard and Soft Real-time Tasks Jonas Flodin, Kai Lampka, Wang Yi Department of Information Technology, Uppsala University Email: {jonas.flodin, kai.lampka, yi}@

Source URL: user.it.uu.se

Using gem5 for DRAM Exploration Presented by: Éder F. Zulian Microelectronic Systems Design Research Group University of Kaiserslautern

Source URL: learning.gem5.org

ATCache: Reducing DRAM cache Latency via a Small SRAM Tag Cache Cheng-Chieh Huang Vijay Nagarajan

Source URL: homepages.inf.ed.ac.uk

DCA: a DRAM-cache-aware DRAM controller Cheng-Chieh Huang Vijay Nagarajan Arpit Joshi

Source URL: homepages.inf.ed.ac.uk

C3D: Mitigating the NUMA Bottleneck via Coherent DRAM Caches Cheng-Chieh Huang Rakesh Kumar Marco Elver Boris Grot Vijay Nagarajan Institute of Computing Systems Architecture University of Edinburgh

Source URL: homepages.inf.ed.ac.uk

DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks Peter Pessl, Daniel Gruss, Clémentine Maurice, Michael Schwarz, and Stefan Mangard, Graz University of Technology https://www.usenix.org/conference/usenixsecurity1

Source URL: www.usenix.org

1 Josiah Royce: Classical American Philosopher; Pragmatist, Phenomenologist, Process Thinker and Advocate for Community Charles Sanders Peirce, William James, Josiah Royce and John Dewey are the usual actors in the dram

Source URL: www.nordprag.org

contributed articles d oi:With scalable high-performance storage entirely in DRAM, RAMCloud will enable a new breed of data-intensive applications.

Source URL: ongardie.net

​SCALING AN ALL FLASH ARRAY ​THE DEVIL IS IN THE DRAM NEIL VACHHARAJANI LEAD SOFTWARE ARCHITECT |

Source URL: www.hpts.ws

Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors Yoongu Kim1 Ross Daly Jeremie Kim1 Chris Fallin Ji Hye Lee1 Donghyuk Lee1 Chris Wilkerson2 Konrad Lai Onur Mutlu1 1

Source URL: users.ece.cmu.edu

• Computer memory
• Computer hardware
• Computing
• Row hammer
• Dynamic random-access memory
• Memory controller
• Random-access memory
• Memory cell
• DDR3 SDRAM
• EDRAM
• Memory refresh
• Sense amplifier