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Computer engineering / Parallel computing / Hardware description language / Microarchitecture / Dataflow / Verilog / Computer architecture / Electronic engineering / Computing


CALIFORNIA STATE SCIENCE FAIR 2015 PROJECT SUMMARY Name(s) Project Number
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Document Date: 2015-04-06 12:55:06

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File Size: 14,44 KB

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Company

RTL / Xilinx / /

IndustryTerm

hardware simulation\synthesis tool / conventional parallel processor / conventional serial processors / conventional serial processor / parallel computing / serial processor / conventional parallel processors / simulation tool / /

Person

Vikram Bhagavatula / /

ProgrammingLanguage

Verilog / /

Technology

serial processor / conventional parallel processors / simulation / Verilog / conventional serial processors / conventional parallel processor / 4x4 DDP processors / DDP processors / conventional serial processor / /

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