server memory systems / memory-intensive applications / server products / memory-sensitive applications / large chips / baseline processor / bank groups / server systems / memory systems / technology scaling advances / earlier technology generations / parallel applications / 3DS technology / memory-bound applications / bank / energy-efficient server-class configuration / microprocessor chip / day memory systems / density memory systems / diverse parallel applications / manufacturing / energy calculations / rank groups / software solution / technology dependent / system operator / power delivery network / /
NaturalFeature
mg ocean / /
Organization
Cornell University / SESC / /
Person
Earthquake / Thomas J. Watson / / /
Position
memory scheduler / mA Data Mining Decision Tree NAS OpenMP Multigrid Solver Conjugate Gradient SPEC OpenMP Shallow water model / model / scheduler / memory controller / controller / programmer / /
Product
Adaptive Refresh / dL1 / /
ProgrammingLanguage
FP / /
ProvinceOrState
Manitoba / Arkansas / /
Technology
Alpha / large capacity DRAM chips / NAND technology / iL1/dL1 MSHR entries iL1/dL1 associativity Memory Disambiguation Coherence protocol / 16 Gb x8 DDR4 DRAM chip / scheduling algorithm / DDR4 DRAM chips / 4 Gb chips / using 3DS technology / 32 Gb DDR4 DRAM chips / PCD algorithm / FR-FCFS scheduling algorithm / 4 Gb chip / dense DRAM chips / 32 Gb DRAM chip / microprocessor chip / Smart Refresh algorithm / Data Mining / high-density DRAM chips / SDRAM / Simulation / DRAM chips / 2.2 DDR4 DRAM Refresh Challenges As technology / 4 Gb DRAM chip / 32 Gb chips / baseline processor / /
Understanding and Mitigating Refresh Overheads in High-Density DDR4 DRAM Systems Janani Mukundan Hillery Hunter