<--- Back to Details
First PageDocument Content
Computer architecture / Classes of computers / Cray-1 / Vector processor / Superscalar / Central processing unit / Cray Y-MP / NEC SX-6 / Computing / Parallel computing / Supercomputers
Date: 1996-09-20 19:00:37
Computer architecture
Classes of computers
Cray-1
Vector processor
Superscalar
Central processing unit
Cray Y-MP
NEC SX-6
Computing
Parallel computing
Supercomputers

Add to Reading List

Source URL: www.eecs.berkeley.edu

Download Document from Source Website

File Size: 51,48 KB

Share Document on Facebook

Similar Documents

Software / Computing / Central processing unit / Array programming languages / Fortran / Vectorization / GNU Compiler Collection / Vector / Processor register / Image tracing

Lecture 13: Vectors William Gropp www.cs.illinois.edu/~wgropp Overview •  Parallelism with the processor

DocID: 1qT3w - View Document

Computing / Software engineering / Central processing unit / Computer programming / Computer memory / Cache / Programming languages / CPU cache / Sparse matrix / Processor register / Fortran / Data

Lecture 4: Modeling Sparse Matrix-Vector Multiply William Gropp www.cs.illinois.edu/~wgropp Sustained Memory Bandwidth

DocID: 1qD59 - View Document

Parallel computing / Computing / Computer programming / Computer architecture / Multicore Association / MCAPI / Manycore processor / Multi-core processor / Embedded system / Vector Fabrics /  B.V.

Multicore Tools SHIM Multicore HW Software-Hardware Interface for Multi-many-core

DocID: 1q8Ws - View Document

Computing / Computer engineering / Computer architecture / Parallel computing / Central processing unit / Cache / Computer memory / CPU cache / Vector processor / Memory access pattern / Memory hierarchy / Processor register

Improving Memory Subsystem Performance using ViVA: Virtual Vector Architecture Joseph Gebis12 ,Leonid Oliker12 , John Shalf1 , Samuel Williams12 ,Katherine Yelick12 1 CRD/NERSC, Lawrence Berkeley National Laboratory Ber

DocID: 1q3Q3 - View Document

Central processing unit / Computing / Computer engineering / Computer architecture / Parallel computing / Processor register / Inter frame / Vector processor / Video compression / ISO standards

A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation Nuno Roma and Leonel Sousa Instituto Superior Técnico / INESC-ID, Lisboa, Portugal Abstract:

DocID: 1pQXh - View Document