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Computer architecture / Parallel computing / Compiler optimizations / Cache / Computer memory / CPU cache / Xeon Phi / Multi-core processor / Xeon / Loop nest optimization / Nehalem / PowerPC A2


Anatomy of High-Performance Many-Threaded Matrix Multiplication Tyler M. Smith∗ , Robert van de Geijn∗ , Mikhail Smelyanskiy† , Jeff R. Hammond‡ and Field G. Van Zee∗ ∗ Institute for Computational Engineerin
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Document Date: 2014-02-10 15:58:29


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File Size: 409,39 KB

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