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 Date: 2009-02-13 05:39:10Cache Compiler optimizations Computing Computer architecture Computer memory Computer engineering Locality of reference Software optimization Cache replacement policies Loop optimization Memory hierarchy Loop interchange |
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Static Prediction of Worst-case Data Cache Performance in the Absence of Base Address Information Diego Andrade, Basilio B. Fraguela and Ram´on Doallo University of A Coru˜na, Spain {dcanosa,basilio,doallo}@udc.es
