clock distribution network / adjacent processing elements / straight-line clock distribution network / e -x2 / clock distsribution network / e-' / e-rZ / signal processing / synchronous systems / boardlevel clock distribution network / e -u2 / large parallel systems / clock signal to chips / /
Organization
Systolic Arrays MARIOS D. DIKAIAKOS AND KENNETH STEIGLITZ Department of ComputerScience / Princeton University / /
Person
KENNETH STEIGLITZ / /
Position
Rt / Fisher / probabilistic model for clock skew / /
Journal of VLSI Signal Processing,2, 1991KluwerAcademicPublishers, Boston. Manufacturedin The Netherlands. Comparison of Tree and Straight-Line Clocking for Long Systolic Arrays MARIOS D. DIKAIAKOS AND K