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Digital electronics / Logic families / Clock signal / CMOS / Logic gate / Transistor / Flip-flop / Clock distribution network / Inverter / Electronic engineering / Electrical engineering / Electromagnetism


Self-timed circuitry for global clocking Scott Fairbanks Cambridge University Abstract We present an apparatus used to distribute a timing reference or clock across the extent of a digital sy
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Document Date: 2005-12-06 10:52:57


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step algorithm / clock distribution solution / billion-plus transistor systems / power distribution systems / open-loop solution / clock network / prevalent clock tree solution / 16mm chip / /

Organization

Cambridge University / /

Person

Scott Fairbanks / Simon Moore / /

Position

state conductor / state-conductor / driver / second driver / RCL model for the necessary wire length / PMOS driver / conductor / first driver / NMOS driver / second token forward / /

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Hawaii / /

Technology

VLSI chips / 16mm chip / simulation / DCG design algorithm / clock capacitance 1nF Chip / seven step algorithm / handshaking protocol / /

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