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Brayton
Results: 169

#	Item
41	SAT-Based Logic Optimization and Resynthesis Alan Mishchenko Robert Brayton Jie-Hong Roland Jiang Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-04-23 22:32:02 Electronic design automation Boolean network Science Mathematics Design Diagrams Formal methods And-inverter graph
42	On Breakable Cyclic Deﬁnitions Jie-Hong R. Jiang, Alan Mishchenko, and Robert K. Brayton Department of Electrical Engineering and Computer Sciences University of California, Berkeley ABSTRACT Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-05-01 20:25:39 Digital typography Western calligraphy Calligraphy Collation Latin-derived alphabet World glyph set Latin alphabets Character encoding Latin script
43	Incremental Sequential Equivalence Checking and Subgraph Isomorphism Sayak Ray Alan Mishchenko Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2009-07-12 14:37:50 Applied mathematics And-inverter graph Electronic design automation Subgraph isomorphism problem Automatic test pattern generation Graph isomorphism Theoretical computer science Mathematics Diagrams
44	Technology Mapping with Boolean Matching, Supergates and Choices Alan Mishchenko Satrajit Chatterjee Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-04-19 22:57:46 Logic synthesis Circuit Standard cell Boolean function Electronic engineering Electronic design automation And-inverter graph
45	Scalably-Verifiable Sequential Synthesis Robert Brayton Alan Mishchenko Department of EECS, University of California, Berkeley Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2007-10-02 14:31:33 Electronic design automation Digital electronics Logic in computer science Electrical circuits And-inverter graph Retiming Automatic test pattern generation Formal verification Combinational logic Electronic engineering Formal methods Theoretical computer science
46	Reducing Structural Bias in Technology Mapping S. Chatterjee A. Mishchenko R. Brayton X. Wang T. Kam Department of EECS Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-07-16 02:15:25 Electronics Diagrams Boolean algebra And-inverter graph Circuit Logic synthesis Topology Boolean function Artificial neuron Electronic engineering Electromagnetism Electronic design automation
47	Efficient Implementation of Property Directed Reachability∗ Niklas Een, Alan Mishchenko, Robert Brayton {een,alanmi,brayton}@eecs.berkeley.edu Berkeley Verification and Synthesis Research Center EECS Department Univers Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2012-06-06 17:57:57 Unit propagation Cube Clause Geometry Euclidean geometry Automated theorem proving
48	FRAIGs: A Unifying Representation for Logic Synthesis and Verification Alan Mishchenko, Satrajit Chatterjee, Roland Jiang, Robert Brayton Department of EECS, University of California, Berkeley {alanmi, satrajit, jiejiang Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-04-01 15:19:32 Boolean algebra Diagrams Digital electronics And-inverter graph Binary decision diagram Logic optimization Model checking Boolean function Logic synthesis Electronic engineering Electronic design automation Formal methods
49	An Integrated Technology Mapping Environment Alan Mishchenko Satrajit Chatterjee Robert Brayton Department of EECS University of California, Berkeley {alanmi, satrajit, brayton}@eecs.berkeley.edu Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-07-16 00:13:15 Integrated circuits Electronic design Placement Logic synthesis Field-programmable gate array Jason Cong Complex programmable logic device Application-specific integrated circuit Electronic engineering Electronics Electronic design automation
50	Scalable and Scalably-Verifiable Sequential Synthesis Alan Mishchenko Michael Case Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-07-28 20:26:28 Electronic design automation Electrical circuits And-inverter graph Diagrams Retiming Automatic test pattern generation Scan chain Combinational logic Sequential logic Electronic engineering Formal methods Digital electronics

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