Back to Results
First PageMeta Content
Block ciphers / Reconfigurable computing / AES implementations / DEAL / Field-programmable gate array / LEX / Xilinx / KHAZAD / Cryptography / Advanced Encryption Standard / Data Encryption Standard


Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications Ga¨el Rouvroy, Franc¸ois-Xavier Standaert, Jean-Jacques Quisquater and Jea
Add to Reading List

Document Date: 2007-11-14 11:09:55


Open Document

File Size: 243,64 KB

Share Result on Facebook

City

New York / /

Company

CAST Inc. / Reconfigurable Hardware / Xilinx / the AES / /

Country

United States / /

Currency

USD / /

/

Facility

National Institute of Standards and Technology / port RAM / i+1 i+1 i+1 We store / FIPS PUB / Prentice Hall / store SB / /

IndustryTerm

decryption algorithm / space efficient solution / low cost encryption/decryption solutions / embedded hardware applications / wireless communication / /

Organization

RIJNDAEL / IMC / National Institute of Standards and Technology / ASIC / National Bureau of Standards / NIST’s AES / Triple DES Using SLAAC-1V FPGA Accelerator Board / /

Person

Jean-Didier Legat / Jean-Jacques Quisquater / Xavier Standaert / P.Baretto / V / /

Position

Colonel / /

Product

Synpllify Pro 7.2 / RAM / done using Synpllify Pro 7.2 / /

ProvinceOrState

New York / /

PublishedMedium

IEEE Transactions on Computers / Lecture Notes in Computer Science / /

Region

Levant / /

TVStation

Kbit / /

Technology

FPGA / RAM / Helion Technology / Accelerator Board / block cipher / Rijndael encryption / Pay TV / Integrated Circuits / Rijndael algorithm / Encryption / Cryptography / ASIC / Gigabit / decryption algorithm / /

URL

http /

SocialTag