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![]() Date: 2014-06-12 14:20:19X86 architecture Cryptographic software AES instruction set Advanced Encryption Standard OpenSSL X86-64 X86 Itanium Xeon Computer architecture Computing Instruction set architectures | Add to Reading List |
![]() | Power-aware Computing: Measurement, Control, and Performance Analysis for Intel Xeon Phi Azzam Haidar∗ , Heike Jagode∗ , Asim YarKhan∗ , Phil Vaccaro∗ , Stanimire Tomov∗ , Jack Dongarra∗†‡ {haidar|jagode|DocID: 1vr39 - View Document |
![]() | Performance and Tuning Considerations for SAS on the Intel Xeon E5 v4 Series Processors and the Vexata VX-100F Storage SystemDocID: 1v2yr - View Document |
![]() | iWARP Support in Scalable Xeon PlatformDocID: 1v0fP - View Document |
![]() | Cotización PLAN XEON E3-2 PERIODO Valor Neto Mensual IVA (19%)DocID: 1uVmN - View Document |
![]() | AMBER: The How, What and Why on an Intel® Xeon Phi™ Perri Needham & Ross Walker (SDSC / UCSD)DocID: 1uONM - View Document |