Adder

Results: 252



#Item
41Presentation brochure  Simulín Simulín Digital Circuit

Presentation brochure Simulín Simulín Digital Circuit

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Source URL: labatc.umh.es

Language: English - Date: 2014-09-01 16:34:10
4214th IEEE Symposium on Computer Arithmetic (ARITH 14), Adelaide, Australia, AprilEfficient VLSI Implementation of Modulo 2n 

14th IEEE Symposium on Computer Arithmetic (ARITH 14), Adelaide, Australia, AprilEfficient VLSI Implementation of Modulo 2n 

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Source URL: www.iis.ee.ethz.ch

Language: English - Date: 2006-05-18 16:42:23
43Faster Secure Two-Party Computation Using Garbled Circuits  Yan Huang David Evans University of Virginia

Faster Secure Two-Party Computation Using Garbled Circuits Yan Huang David Evans University of Virginia

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Source URL: www.usenix.org

Language: English - Date: 2011-06-09 13:31:32
44Proceedings 37th Asilomar Conference on Signals, Systems, and Computers, November 2003  © 2003 IEEE Optimized Synthesis of Sum-of-Products Reto Zimmermann and David Q. Tran

Proceedings 37th Asilomar Conference on Signals, Systems, and Computers, November 2003 © 2003 IEEE Optimized Synthesis of Sum-of-Products Reto Zimmermann and David Q. Tran

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Source URL: www.iis.ee.ethz.ch

Language: English - Date: 2003-11-20 21:11:27
45LOGIC MODULES INTRODUCTION EXPANSION ACTIVITY

LOGIC MODULES INTRODUCTION EXPANSION ACTIVITY

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Source URL: s3.amazonaws.com

Language: English - Date: 2014-05-06 16:08:52
46CS61CL Machine Structures Lec 8 – State and Register Transfers David Culler Electrical Engineering and Computer Sciences University of California, Berkeley

CS61CL Machine Structures Lec 8 – State and Register Transfers David Culler Electrical Engineering and Computer Sciences University of California, Berkeley

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Source URL: inst.eecs.berkeley.edu

Language: English - Date: 2009-10-21 17:45:09
47Diss. ETH NoBinary Adder Architectures for Cell-Based VLSI and their Synthesis A dissertation submitted to the

Diss. ETH NoBinary Adder Architectures for Cell-Based VLSI and their Synthesis A dissertation submitted to the

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Source URL: www.iis.ee.ethz.ch

Language: English - Date: 2006-03-07 18:18:41
48Diss. ETH NoBinary Adder Architectures for Cell-Based VLSI and their Synthesis A dissertation submitted to the

Diss. ETH NoBinary Adder Architectures for Cell-Based VLSI and their Synthesis A dissertation submitted to the

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Source URL: www.iis.ee.ethz.ch

Language: English - Date: 2006-03-07 18:19:07
492009 19th IEEE International Symposium on Computer Arithmetic  Datapath Synthesis for Standard-Cell Design Reto Zimmermann DesignWare, Solutions Group Synopsys Switzerland LLC, 8050 Zurich, Switzerland

2009 19th IEEE International Symposium on Computer Arithmetic Datapath Synthesis for Standard-Cell Design Reto Zimmermann DesignWare, Solutions Group Synopsys Switzerland LLC, 8050 Zurich, Switzerland

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Source URL: www.iis.ee.ethz.ch

Language: English - Date: 2009-09-17 16:31:54
50

PDF Document

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Source URL: www.iis.ee.ethz.ch

Language: English - Date: 2006-03-07 18:40:56